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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [minsoc_startup/] [OR1K_startup_generic.v] - Rev 109

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109 Creating a branche for release candidate 1.0. rfajardo 3987d 13h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4755d 21h /minsoc/branches/rc-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v

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