OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [xilinx_dcm.v] - Rev 109

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
109 Creating a branche for release candidate 1.0. rfajardo 4736d 06h /minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4786d 09h /minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 4916d 15h /minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.