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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] [xilinx_dcm.v] - Rev 114

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109 Creating a branche for release candidate 1.0. rfajardo 3857d 19h /minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3907d 22h /minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 4038d 05h /minsoc/branches/rc-1.0/rtl/verilog/xilinx_dcm.v

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