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[/] [minsoc/] [branches/] [rc-1.0/] [sim/] [modelsim/] [run_sim.sh] - Rev 133

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Rev Log message Author Age Path
133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.
rfajardo 3270d 17h /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh
132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 3274d 12h /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh
109 Creating a branche for release candidate 1.0. rfajardo 3282d 06h /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3451d 16h /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh

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