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101 Documentation, wiki's address updated. rfajardo 4572d 09h /minsoc/branches/rc-1.0
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 4581d 07h /minsoc/branches/rc-1.0
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4581d 07h /minsoc/branches/rc-1.0
98 Removing deprecated minsoc_top.qsf file. rfajardo 4581d 07h /minsoc/branches/rc-1.0
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4581d 07h /minsoc/branches/rc-1.0
96 Some files needed for Altera synthesis javieralso 4581d 18h /minsoc/branches/rc-1.0
95 Makefile for Altera FPGAs fixed javieralso 4582d 21h /minsoc/branches/rc-1.0
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4585d 06h /minsoc/branches/rc-1.0
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4585d 09h /minsoc/branches/rc-1.0
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4586d 07h /minsoc/branches/rc-1.0

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