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[/] [minsoc/] [branches/] [verilator/] [prj/] [Makefile] - Rev 109

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109 Creating a branche for release candidate 1.0. rfajardo 4537d 16h /minsoc/branches/verilator/prj/Makefile
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 4545d 02h /minsoc/branches/verilator/prj/Makefile
96 Some files needed for Altera synthesis javieralso 4582d 14h /minsoc/branches/verilator/prj/Makefile
95 Makefile for Altera FPGAs fixed javieralso 4583d 17h /minsoc/branches/verilator/prj/Makefile
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4587d 19h /minsoc/branches/verilator/prj/Makefile
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4587d 20h /minsoc/branches/verilator/prj/Makefile

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