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[/] [minsoc/] [branches/] [verilator/] [prj/] [altera/] - Rev 139


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Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 3964d 11h /minsoc/branches/verilator/prj/altera/
109 Creating a branche for release candidate 1.0. rfajardo 3991d 02h /minsoc/branches/verilator/prj/altera/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4035d 13h /minsoc/branches/verilator/prj/altera/
96 Some files needed for Altera synthesis javieralso 4035d 23h /minsoc/branches/verilator/prj/altera/
95 Makefile for Altera FPGAs fixed javieralso 4037d 03h /minsoc/branches/verilator/prj/altera/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4039d 11h /minsoc/branches/verilator/prj/altera/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4039d 14h /minsoc/branches/verilator/prj/altera/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4041d 06h /minsoc/branches/verilator/prj/altera/

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