URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [scripts/] - Rev 104

Rev	Log message	Author	Age	Path
104	Enabling modelsim simulation for current project definition. vhdl and verilog projects have to be separated: -prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS. -Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently. -prj/scripts/simprj.sh splitted in: -simvhdl.sh -simverilog.sh (they generate the input files in the right format for simulation tools)	rfajardo	4572d 04h	/minsoc/branches/verilator/prj/scripts/
96	Some files needed for Altera synthesis	javieralso	4609d 17h	/minsoc/branches/verilator/prj/scripts/
91	prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found.	rfajardo	4614d 06h	/minsoc/branches/verilator/prj/scripts/
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4614d 22h	/minsoc/branches/verilator/prj/scripts/
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4614d 23h	/minsoc/branches/verilator/prj/scripts/