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[/] [minsoc/] [branches/] [verilator/] [rtl/] [verilog/] [timescale.v] - Rev 139

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Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 4510d 22h /minsoc/branches/verilator/rtl/verilog/timescale.v
109 Creating a branche for release candidate 1.0. rfajardo 4537d 12h /minsoc/branches/verilator/rtl/verilog/timescale.v
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 4706d 22h /minsoc/branches/verilator/rtl/verilog/timescale.v

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