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[/] [minsoc/] [branches/] [verilator/] [rtl/] [verilog/] [xilinx_dcm.v] - Rev 140

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Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 3832d 04h /minsoc/branches/verilator/rtl/verilog/xilinx_dcm.v
109 Creating a branche for release candidate 1.0. rfajardo 3858d 18h /minsoc/branches/verilator/rtl/verilog/xilinx_dcm.v
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3908d 21h /minsoc/branches/verilator/rtl/verilog/xilinx_dcm.v
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 4039d 04h /minsoc/branches/verilator/rtl/verilog/xilinx_dcm.v

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