URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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[/] [minsoc/] [branches/] [verilator/] [sim/] [verilator/] [generate_verilator_bench] - Rev 140

Rev	Log message	Author	Age	Path
140	Including required modules for verilator simulation.	rfajardo	4532d 04h	/minsoc/branches/verilator/sim/verilator/generate_verilator_bench