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Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 4759d 05h /minsoc/branches/verilator/syn/altera/
109 Creating a branche for release candidate 1.0. rfajardo 4785d 20h /minsoc/branches/verilator/syn/altera/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.
rfajardo 4786d 02h /minsoc/branches/verilator/syn/altera/
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 4830d 06h /minsoc/branches/verilator/syn/altera/
98 Removing deprecated minsoc_top.qsf file. rfajardo 4830d 07h /minsoc/branches/verilator/syn/altera/
95 Makefile for Altera FPGAs fixed javieralso 4831d 21h /minsoc/branches/verilator/syn/altera/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4834d 08h /minsoc/branches/verilator/syn/altera/

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