OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [utils/] [setup/] [configure.sh] - Rev 139

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
139 Creating a verilator branche. rfajardo 4707d 22h /minsoc/branches/verilator/utils/setup/configure.sh
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.
rfajardo 4733d 13h /minsoc/branches/verilator/utils/setup/configure.sh
115 configure.sh script dir aware.
minsoc-install.sh logging to script dir.
rfajardo 4733d 18h /minsoc/branches/verilator/utils/setup/configure.sh
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files
rfajardo 4733d 19h /minsoc/branches/verilator/utils/setup/configure.sh
112 Updating installation & configuration scripts. rfajardo 4734d 10h /minsoc/branches/verilator/utils/setup/configure.sh
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1
rfajardo 4734d 11h /minsoc/branches/verilator/utils/setup/configure.sh

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.