OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches] - Rev 131

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 4916d 12h /minsoc/branches
130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 4916d 14h /minsoc/branches
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready		 rfajardo 4917d 01h /minsoc/branches
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 4917d 02h /minsoc/branches
127 Removing redundant simulation output. rfajardo 4917d 08h /minsoc/branches
126 Updating information about simulation time for Ethernet test. rfajardo 4917d 08h /minsoc/branches
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 4917d 08h /minsoc/branches
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 4917d 10h /minsoc/branches
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 4917d 15h /minsoc/branches
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 4923d 04h /minsoc/branches
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.		 rfajardo 4923d 06h /minsoc/branches
120 ethmac.prj: a file was missing rfajardo 4923d 09h /minsoc/branches
119 Tricking Subversion to accept bat files that are now executable. rfajardo 4923d 09h /minsoc/branches
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 4923d 09h /minsoc/branches
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 4923d 10h /minsoc/branches
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 4923d 11h /minsoc/branches
115 configure.sh script dir aware.
minsoc-install.sh logging to script dir.		 rfajardo 4923d 11h /minsoc/branches
114 Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from.		 rfajardo 4923d 12h /minsoc/branches
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files		 rfajardo 4923d 12h /minsoc/branches
112 Updating installation & configuration scripts. rfajardo 4924d 03h /minsoc/branches

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.