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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Rev 141

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Rev	Log message	Author	Age	Path
42	Tagging release 0.9 of MinSoC.	rfajardo	4783d 22h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
28	1) Period calculations through 1/freq on testbench use now a numerator definition in order to extract nano seconds of the divisions. Previously the number 1e9 was being repeatedly typed as numerator, now FREQ_NUM_FOR_NS is used. 2) There is a possibility of enabling the GENERIC_CLOCK_DIVISION for the testbench, so that you can test the outcome of different system clock inputs and internal clock adjustments. To do so, NO_CLOCK_DIVISION definition of minsoc_bench_defines.v has to be commented out. -This also requested the initialization of the internal registers clk_int and clock_divisor of the minsoc_clock_manager.v, this is made by the testbench in case the NO_CLOCK_DIVISION definition is NOT defined. 3) Howto part of implementing Ethernet for the Spartan3E Starter Kit has been completely described. (Chapter 7, subitem 3)	rfajardo	5097d 22h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
17	Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v. send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart) If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.	rfajardo	5266d 22h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
11	External interrupt processing was being run multiple times because: -external level interrupts have to be cleared -internal interrupt status register has to be cleared Since internal interrupt status register was being cleared before external level interrupts clearance, these internal interrupt status was being overwritten inbetween. Solution: -move status register reset to end of interrupt handler instead of beginning. Testbench signal uart_srx initialized now.	rfajardo	5291d 22h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
10	Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v. With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers. minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary.	rfajardo	5305d 22h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
9	Tiny change to testbench gain: -uart_srx is now reg for future testbench serial input to SoC.	rfajardo	5307d 20h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
8	Cosmetic changes to minsoc_bench.v: -reset and clock initialization are included into the main initial block, it had an own block before	rfajardo	5307d 20h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
4	minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary. jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it. Documentation now includes: -vpi module compilation -gdb patch for adv_jtag_bridge -ideas for future work on minsoc (To Do v.2)	rfajardo	5323d 02h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5327d 01h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v

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