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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_memory_model.v] - Rev 160

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42 Tagging release 0.9 of MinSoC. rfajardo 4951d 03h /minsoc/tags/release-0.9/bench/verilog/minsoc_memory_model.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 5494d 05h /minsoc/tags/release-0.9/bench/verilog/minsoc_memory_model.v

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