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[/] [minsoc/] [tags/] [release-0.9/] [rtl/] [verilog/] [minsoc_onchip_ram.v] - Rev 6

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6 No implementation relevant changes.

Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.

Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.
rfajardo 5295d 09h /minsoc/tags/release-0.9/rtl/verilog/minsoc_onchip_ram.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 5305d 07h /minsoc/tags/release-0.9/rtl/verilog/minsoc_onchip_ram.v

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