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[/] [minsoc/] [tags/] [release-1.0/] - Rev 172

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Rev Log message Author Age Path
172 Reverting changes to tag. Tags should never be changed. rfajardo 2770d 12h /minsoc/tags/release-1.0/
171 Script for Minsoc deployment javieralso 2798d 18h /minsoc/tags/release-1.0/
169 Changed all links to minsoc.com/dep/v.1.0/ to solve the issues caused by sourceforge.com. ConX. 2838d 16h /minsoc/tags/release-1.0/
151 Creating tag release-1.0 from revision 150 of branches/rc-1.0. rfajardo 3217d 20h /minsoc/tags/release-1.0/
150 Updating installation script to retrieve minsoc from tags/release-1.0. rfajardo 3217d 20h /minsoc/branches/rc-1.0/
148 Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness. rfajardo 3222d 17h /minsoc/branches/rc-1.0/
147 Updating minsoc_bench.v to correctly acquire uart data.

Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
-Eth and Uart firmwares also had a carriage return after the end of line, also removed.

Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT

run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.

minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.
rfajardo 3222d 18h /minsoc/branches/rc-1.0/
146 Importing 'Xilinx Microblaze Dev. Kit 1600E Edition' board configuration directory. ConX. 3223d 00h /minsoc/branches/rc-1.0/
145 minsoc_bench_core.v and minsoc_bench_clock.v left only on verilator branche. It will develop there until it is ported for inclusion into trunk. RC-1.0 is now clean of it. rfajardo 3223d 09h /minsoc/branches/rc-1.0/
143 Compiling firmwares in board configuration scripts instead of on global minsoc setup. rfajardo 3223d 20h /minsoc/branches/rc-1.0/
138 DIR_TO_INSTALL creation using wizard ConX. 3224d 09h /minsoc/branches/rc-1.0/
137 Removing uncomplete support for ml509 and not working support for spartan3e_starter_kit_eth (area constraint cannot be reached). rfajardo 3224d 20h /minsoc/branches/rc-1.0/
136 Installation on Ubuntu-11.10 has shown that a binary called makeinfo is required to install GDB. This binary can be installed on Ubuntu by installing the package texinfo. rfajardo 3231d 15h /minsoc/branches/rc-1.0/
134 run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench. rfajardo 3238d 19h /minsoc/branches/rc-1.0/
133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.
rfajardo 3238d 21h /minsoc/branches/rc-1.0/
132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 3242d 16h /minsoc/branches/rc-1.0/
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 3242d 17h /minsoc/branches/rc-1.0/
130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 3242d 19h /minsoc/branches/rc-1.0/
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready
rfajardo 3243d 06h /minsoc/branches/rc-1.0/
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 3243d 07h /minsoc/branches/rc-1.0/
127 Removing redundant simulation output. rfajardo 3243d 13h /minsoc/branches/rc-1.0/
126 Updating information about simulation time for Ethernet test. rfajardo 3243d 13h /minsoc/branches/rc-1.0/
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 3243d 13h /minsoc/branches/rc-1.0/
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 3243d 15h /minsoc/branches/rc-1.0/
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 3243d 20h /minsoc/branches/rc-1.0/
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 3249d 09h /minsoc/branches/rc-1.0/
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.
rfajardo 3249d 11h /minsoc/branches/rc-1.0/
120 ethmac.prj: a file was missing rfajardo 3249d 14h /minsoc/branches/rc-1.0/
119 Tricking Subversion to accept bat files that are now executable. rfajardo 3249d 14h /minsoc/branches/rc-1.0/
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 3249d 14h /minsoc/branches/rc-1.0/

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