| Rev |
Log message |
Author |
Age |
Path |
| 151 |
Creating tag release-1.0 from revision 150 of branches/rc-1.0. |
rfajardo |
4703d 06h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 147 |
Updating minsoc_bench.v to correctly acquire uart data.
Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
-Eth and Uart firmwares also had a carriage return after the end of line, also removed.
Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT
run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.
minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run. |
rfajardo |
4708d 04h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 143 |
Compiling firmwares in board configuration scripts instead of on global minsoc setup. |
rfajardo |
4709d 06h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 124 |
Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. |
rfajardo |
4729d 01h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 116 |
Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. |
rfajardo |
4735d 02h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 110 |
Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure
-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0
-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.
-prj/src: or1200_top.prj downdated to definition of or1200_v1 |
rfajardo |
4735d 19h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4735d 21h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4736d 08h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4780d 07h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4780d 08h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4780d 19h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4781d 22h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4784d 09h |
/minsoc/tags/release-1.0/backend/altera_3c25_board/ |
