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151 Creating tag release-1.0 from revision 150 of branches/rc-1.0. rfajardo 3225d 02h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
147 Updating minsoc_bench.v to correctly acquire uart data.

Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
-Eth and Uart firmwares also had a carriage return after the end of line, also removed.

Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT

run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.

minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.
rfajardo 3230d 00h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
143 Compiling firmwares in board configuration scripts instead of on global minsoc setup. rfajardo 3231d 01h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 3250d 21h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 3256d 20h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 3256d 21h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 3256d 22h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files
rfajardo 3256d 23h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
109 Creating a branche for release candidate 1.0. rfajardo 3257d 17h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3258d 03h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3302d 04h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3307d 03h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3307d 20h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
87 Synchronizing scripts to behave exactly the same. rfajardo 3307d 21h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
86 Updating configure script messages. rfajardo 3307d 21h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3307d 21h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
80 Establishing a better Makefile system for firmwares. rfajardo 3326d 01h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3427d 02h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
69 backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.

backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 3431d 18h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/
66 spartan3e_starter_kit requires special configuration of or1200_r3.

For that, configure script was specially adapted and that is reported on script execution.

For release-1.0 of MinSoC this should not be required, because or1200_r1 already has the
required configuration.
rfajardo 3433d 23h /minsoc/tags/release-1.0/backend/spartan3e_starter_kit/

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