| Rev |
Log message |
Author |
Age |
Path |
| 151 |
Creating tag release-1.0 from revision 150 of branches/rc-1.0. |
rfajardo |
4758d 00h |
/minsoc/tags/release-1.0/bench/ |
| 148 |
Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness. |
rfajardo |
4762d 20h |
/minsoc/branches/rc-1.0/bench/ |
| 147 |
Updating minsoc_bench.v to correctly acquire uart data.
Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
-Eth and Uart firmwares also had a carriage return after the end of line, also removed.
Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT
run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.
minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run. |
rfajardo |
4762d 22h |
/minsoc/branches/rc-1.0/bench/ |
| 145 |
minsoc_bench_core.v and minsoc_bench_clock.v left only on verilator branche. It will develop there until it is ported for inclusion into trunk. RC-1.0 is now clean of it. |
rfajardo |
4763d 13h |
/minsoc/branches/rc-1.0/bench/ |
| 133 |
Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.
Applying Rubén Diez patch to avoid warnings on firmware load for simulation. |
rfajardo |
4779d 01h |
/minsoc/branches/rc-1.0/bench/ |
| 131 |
Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. |
rfajardo |
4782d 20h |
/minsoc/branches/rc-1.0/bench/ |
| 130 |
minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. |
rfajardo |
4782d 23h |
/minsoc/branches/rc-1.0/bench/ |
| 129 |
Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready |
rfajardo |
4783d 10h |
/minsoc/branches/rc-1.0/bench/ |
| 128 |
Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. |
rfajardo |
4783d 11h |
/minsoc/branches/rc-1.0/bench/ |
| 127 |
Removing redundant simulation output. |
rfajardo |
4783d 17h |
/minsoc/branches/rc-1.0/bench/ |
| 126 |
Updating information about simulation time for Ethernet test. |
rfajardo |
4783d 17h |
/minsoc/branches/rc-1.0/bench/ |
| 125 |
Adjusting testbench messages. Creating tasks for firmware tests. |
rfajardo |
4783d 17h |
/minsoc/branches/rc-1.0/bench/ |
| 124 |
Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. |
rfajardo |
4783d 19h |
/minsoc/branches/rc-1.0/bench/ |
| 123 |
Renaming reg final to firmware_size. Final is a keyword for Verilator. |
rfajardo |
4784d 00h |
/minsoc/branches/rc-1.0/bench/ |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4790d 15h |
/minsoc/branches/rc-1.0/bench/ |
| 71 |
Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v
modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a
Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now. |
rfajardo |
4960d 00h |
/minsoc/trunk/bench/ |
| 69 |
backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.
They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.
backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet. |
rfajardo |
4964d 16h |
/minsoc/trunk/bench/ |
| 64 |
firmware makefiles:
-every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you.
-TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually.
Makefile system for synthesis:
-the dependency for every implementation step has been checked and is working fine.
-Makefile plus support files have been moved to minsoc/syn/src
-make usage is still under syn through files generated by backend bashscripts
Backend:
-files under backend are target specific files used for the system to work
-firmware compilation
-system simulation
-system implementation
-This directory is populated by visiting one of its subdirectories and typing ./configure
backend/spartan3a_dsp_kit:
-working on FPGA
backend/spartan3e_starter_kit:
-has to be tested
backend/ml509:
-missing files have to be copied and adapted, configure script has to be copied and adapted
backend/std:
-include files necessary for firmware compilation and system configuration
-it does not include files for synthesis and is not synthesizable |
rfajardo |
4966d 23h |
/minsoc/trunk/bench/ |
| 60 |
Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.
minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition. |
rfajardo |
4971d 12h |
/minsoc/trunk/bench/ |
| 59 |
undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of minsoc_defines.v. Instead, the testbench now works with the right reset level to avoid the implementation ordering problem. |
rfajardo |
4971d 12h |
/minsoc/trunk/bench/ |
