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[/] [minsoc/] [tags/] [release-1.0/] [utils/] [setup/] - Rev 172

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Rev Log message Author Age Path
172 Reverting changes to tag. Tags should never be changed. rfajardo 4082d 19h /minsoc/tags/release-1.0/utils/setup/
171 Script for Minsoc deployment javieralso 4111d 01h /minsoc/tags/release-1.0/utils/setup/
169 Changed all links to minsoc.com/dep/v.1.0/ to solve the issues caused by sourceforge.com. ConX. 4150d 23h /minsoc/tags/release-1.0/utils/setup/
151 Creating tag release-1.0 from revision 150 of branches/rc-1.0. rfajardo 4530d 03h /minsoc/tags/release-1.0/utils/setup/
150 Updating installation script to retrieve minsoc from tags/release-1.0. rfajardo 4530d 03h /minsoc/tags/release-1.0/utils/setup/
147 Updating minsoc_bench.v to correctly acquire uart data.

Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
-Eth and Uart firmwares also had a carriage return after the end of line, also removed.

Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT

run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.

minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.		 rfajardo 4535d 01h /minsoc/tags/release-1.0/utils/setup/
143 Compiling firmwares in board configuration scripts instead of on global minsoc setup. rfajardo 4536d 02h /minsoc/tags/release-1.0/utils/setup/
138 DIR_TO_INSTALL creation using wizard ConX. 4536d 16h /minsoc/tags/release-1.0/utils/setup/
136 Installation on Ubuntu-11.10 has shown that a binary called makeinfo is required to install GDB. This binary can be installed on Ubuntu by installing the package texinfo. rfajardo 4543d 22h /minsoc/tags/release-1.0/utils/setup/
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 4561d 16h /minsoc/tags/release-1.0/utils/setup/
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.		 rfajardo 4561d 18h /minsoc/tags/release-1.0/utils/setup/
115 configure.sh script dir aware.
minsoc-install.sh logging to script dir.		 rfajardo 4561d 23h /minsoc/tags/release-1.0/utils/setup/
114 Installation and Configuration scripts can be run out of any directory.
They assume they are going to process the files and directories found in the directory they are run from.		 rfajardo 4561d 23h /minsoc/tags/release-1.0/utils/setup/
113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files		 rfajardo 4562d 00h /minsoc/tags/release-1.0/utils/setup/
112 Updating installation & configuration scripts. rfajardo 4562d 15h /minsoc/tags/release-1.0/utils/setup/
111 minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh rfajardo 4562d 16h /minsoc/tags/release-1.0/utils/setup/
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1		 rfajardo 4562d 16h /minsoc/tags/release-1.0/utils/setup/
109 Creating a branche for release candidate 1.0. rfajardo 4562d 18h /minsoc/tags/release-1.0/utils/setup/
106 Installation script was checking the ENV variable before setting it. rfajardo 4563d 02h /minsoc/tags/release-1.0/utils/setup/
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 4572d 18h /minsoc/tags/release-1.0/utils/setup/

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