| Rev |
Log message |
Author |
Age |
Path |
| 108 |
Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.
Icarus Verilog and Altera synthesis are working as well. Job done! |
rfajardo |
4790d 06h |
/minsoc/trunk/ |
| 107 |
Adding setup batch script for Altera synthesis on Windows.
prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.
Maybe the other scripts have to be updated too. This will be checked soon. |
rfajardo |
4790d 09h |
/minsoc/trunk/ |
| 106 |
Installation script was checking the ENV variable before setting it. |
rfajardo |
4790d 12h |
/minsoc/trunk/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4790d 13h |
/minsoc/trunk/ |
| 104 |
Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools) |
rfajardo |
4797d 12h |
/minsoc/trunk/ |
| 103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
4800d 03h |
/minsoc/trunk/ |
| 102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4800d 03h |
/minsoc/trunk/ |
| 101 |
Documentation, wiki's address updated. |
rfajardo |
4825d 15h |
/minsoc/trunk/ |
| 100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
4834d 13h |
/minsoc/trunk/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4834d 13h |
/minsoc/trunk/ |
| 98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
4834d 14h |
/minsoc/trunk/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4834d 14h |
/minsoc/trunk/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4835d 01h |
/minsoc/trunk/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4836d 04h |
/minsoc/trunk/ |
| 94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4838d 12h |
/minsoc/trunk/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4838d 15h |
/minsoc/trunk/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4839d 13h |
/minsoc/trunk/ |
| 91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4839d 14h |
/minsoc/trunk/ |
| 90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4840d 05h |
/minsoc/trunk/ |
| 89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
4840d 05h |
/minsoc/trunk/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4840d 06h |
/minsoc/trunk/ |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4840d 07h |
/minsoc/trunk/ |
| 86 |
Updating configure script messages. |
rfajardo |
4840d 07h |
/minsoc/trunk/ |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4840d 07h |
/minsoc/trunk/ |
| 84 |
syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v |
rfajardo |
4841d 08h |
/minsoc/trunk/ |
| 83 |
minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. |
rfajardo |
4852d 13h |
/minsoc/trunk/ |
| 82 |
minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. |
rfajardo |
4855d 12h |
/minsoc/trunk/ |
| 81 |
Installation script complete, nice text feedback, output logs and better execution order. |
rfajardo |
4855d 23h |
/minsoc/trunk/ |
| 80 |
Establishing a better Makefile system for firmwares. |
rfajardo |
4858d 12h |
/minsoc/trunk/ |
| 79 |
minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated |
rfajardo |
4859d 04h |
/minsoc/trunk/ |
