| Rev |
Log message |
Author |
Age |
Path |
| 154 |
Modified to use the new autotools support in the advanced debug system v3.0. |
nyawn |
4915d 21h |
/minsoc/trunk/ |
| 149 |
Merging differences of release candidate 1.0 revision 140:148 with trunk. |
rfajardo |
4948d 11h |
/minsoc/trunk/ |
| 144 |
Updating configure scripts. Calling make into the right directories now. |
rfajardo |
4954d 10h |
/minsoc/trunk/ |
| 142 |
Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.
backend/xxx/configure: compiling firmwares here now. |
rfajardo |
4954d 10h |
/minsoc/trunk/ |
| 141 |
Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. |
rfajardo |
4954d 10h |
/minsoc/trunk/ |
| 135 |
Installation on Ubuntu-11.10 has shown that package texinfo is required to compiled GDB. This package installs the binary makeinfo. |
rfajardo |
4962d 06h |
/minsoc/trunk/ |
| 108 |
Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.
Icarus Verilog and Altera synthesis are working as well. Job done! |
rfajardo |
4981d 04h |
/minsoc/trunk/ |
| 107 |
Adding setup batch script for Altera synthesis on Windows.
prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.
Maybe the other scripts have to be updated too. This will be checked soon. |
rfajardo |
4981d 07h |
/minsoc/trunk/ |
| 106 |
Installation script was checking the ENV variable before setting it. |
rfajardo |
4981d 10h |
/minsoc/trunk/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4981d 12h |
/minsoc/trunk/ |
| 104 |
Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools) |
rfajardo |
4988d 10h |
/minsoc/trunk/ |
| 103 |
But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. |
rfajardo |
4991d 02h |
/minsoc/trunk/ |
| 102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4991d 02h |
/minsoc/trunk/ |
| 101 |
Documentation, wiki's address updated. |
rfajardo |
5016d 14h |
/minsoc/trunk/ |
| 100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
5025d 11h |
/minsoc/trunk/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
5025d 11h |
/minsoc/trunk/ |
| 98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
5025d 12h |
/minsoc/trunk/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
5025d 12h |
/minsoc/trunk/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
5025d 23h |
/minsoc/trunk/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
5027d 02h |
/minsoc/trunk/ |
| 94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
5029d 11h |
/minsoc/trunk/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
5029d 13h |
/minsoc/trunk/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
5030d 11h |
/minsoc/trunk/ |
| 91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
5030d 12h |
/minsoc/trunk/ |
| 90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
5031d 04h |
/minsoc/trunk/ |
| 89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
5031d 04h |
/minsoc/trunk/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
5031d 04h |
/minsoc/trunk/ |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
5031d 05h |
/minsoc/trunk/ |
| 86 |
Updating configure script messages. |
rfajardo |
5031d 05h |
/minsoc/trunk/ |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
5031d 05h |
/minsoc/trunk/ |
