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Rev Log message Author Age Path
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3906d 12h /minsoc/trunk/
96 Some files needed for Altera synthesis javieralso 3906d 23h /minsoc/trunk/
95 Makefile for Altera FPGAs fixed javieralso 3908d 02h /minsoc/trunk/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 3910d 10h /minsoc/trunk/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3910d 13h /minsoc/trunk/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3911d 11h /minsoc/trunk/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3911d 12h /minsoc/trunk/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 3912d 03h /minsoc/trunk/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 3912d 04h /minsoc/trunk/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3912d 04h /minsoc/trunk/

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