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157 Removed obsolete file; the changes in this version have been merged into
the mainline advanced debug system version 3.0 and higher.		 nyawn 4492d 08h /minsoc/trunk
156 Added hardware watchpoint indicators to debug unit break input, to allow
the debugger to break when a hardware watchpoint is triggered.		 nyawn 4492d 08h /minsoc/trunk
155 Decreased wait time, for faster simulations. nyawn 4492d 08h /minsoc/trunk
154 Modified to use the new autotools support in the advanced debug system v3.0. nyawn 4492d 08h /minsoc/trunk
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 4524d 23h /minsoc/trunk
144 Updating configure scripts. Calling make into the right directories now. rfajardo 4530d 22h /minsoc/trunk
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.		 rfajardo 4530d 22h /minsoc/trunk
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 4530d 22h /minsoc/trunk
135 Installation on Ubuntu-11.10 has shown that package texinfo is required to compiled GDB. This package installs the binary makeinfo. rfajardo 4538d 18h /minsoc/trunk
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!		 rfajardo 4557d 16h /minsoc/trunk
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.		 rfajardo 4557d 19h /minsoc/trunk
106 Installation script was checking the ENV variable before setting it. rfajardo 4557d 22h /minsoc/trunk
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 4558d 00h /minsoc/trunk
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4564d 22h /minsoc/trunk
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 4567d 13h /minsoc/trunk
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 4567d 13h /minsoc/trunk
101 Documentation, wiki's address updated. rfajardo 4593d 01h /minsoc/trunk
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 4601d 23h /minsoc/trunk
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4601d 23h /minsoc/trunk
98 Removing deprecated minsoc_top.qsf file. rfajardo 4602d 00h /minsoc/trunk

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