| Rev |
Log message |
Author |
Age |
Path |
| 166 |
Turning on warnings for genera_bench.
Updating minsoc-install.sh to work better with directories and working around a missing inclusion of libftdi autotools. http://opencores.org/forum,OpenRISC,0,4685,1 |
rfajardo |
3469d 22h |
/minsoc/trunk/ |
| 165 |
Board contribution: nexys2_1200 (Thanks to Johan Granath)
spartan3e_starter_kit_eth/minsoc_bench_defines.v: deprecated definition updated |
rfajardo |
3486d 23h |
/minsoc/trunk/ |
| 164 |
Updating width of minsoc_tc_top.v for Wishbone B3 compliance. This file has never worked. This solves at least the bug that some signals were not being routed through. |
rfajardo |
3551d 15h |
/minsoc/trunk/ |
| 163 |
Adjusting internal initiator array widths. They were 1 bit too large. Thanks to R. Diez report.
These arrays abstract the complete initiator inputs. This way it is easier to route and arbiter using a single input.
Also removing 2 sequential delays. I didn't design them, so I can't tell if they were really useful/good. |
rfajardo |
3557d 22h |
/minsoc/trunk/ |
| 162 |
Tasks don't have parenthesis. This is only used for ports on modules. This was a mistake from my part. |
rfajardo |
3563d 17h |
/minsoc/trunk/ |
| 161 |
Correcting configure parameters of adv_jtag_bridge on installation script. |
rfajardo |
3576d 20h |
/minsoc/trunk/ |
| 160 |
Typo in minsoc-install.sh script. Adv_jtag_bridge was not configuring correctly. |
rfajardo |
3576d 20h |
/minsoc/trunk/ |
| 159 |
Updated constraint file for de2_115 board. (Richard Hasha) |
rfajardo |
3576d 21h |
/minsoc/trunk/ |
| 158 |
Adding de2_115_board port, thanks to Richard Hasha.
Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.
Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.
Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.
prj/srcs extended to include jsp and interconnec_defines.v.
spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now. |
rfajardo |
3578d 13h |
/minsoc/trunk/ |
| 157 |
Removed obsolete file; the changes in this version have been merged into
the mainline advanced debug system version 3.0 and higher. |
nyawn |
3584d 08h |
/minsoc/trunk/ |
| 156 |
Added hardware watchpoint indicators to debug unit break input, to allow
the debugger to break when a hardware watchpoint is triggered. |
nyawn |
3584d 08h |
/minsoc/trunk/ |
| 155 |
Decreased wait time, for faster simulations. |
nyawn |
3584d 08h |
/minsoc/trunk/ |
| 154 |
Modified to use the new autotools support in the advanced debug system v3.0. |
nyawn |
3584d 08h |
/minsoc/trunk/ |
| 149 |
Merging differences of release candidate 1.0 revision 140:148 with trunk. |
rfajardo |
3616d 22h |
/minsoc/trunk/ |
| 144 |
Updating configure scripts. Calling make into the right directories now. |
rfajardo |
3622d 21h |
/minsoc/trunk/ |
| 142 |
Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.
backend/xxx/configure: compiling firmwares here now. |
rfajardo |
3622d 21h |
/minsoc/trunk/ |
| 141 |
Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. |
rfajardo |
3622d 22h |
/minsoc/trunk/ |
| 135 |
Installation on Ubuntu-11.10 has shown that package texinfo is required to compiled GDB. This package installs the binary makeinfo. |
rfajardo |
3630d 17h |
/minsoc/trunk/ |
| 108 |
Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.
Icarus Verilog and Altera synthesis are working as well. Job done! |
rfajardo |
3649d 16h |
/minsoc/trunk/ |
| 107 |
Adding setup batch script for Altera synthesis on Windows.
prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.
Maybe the other scripts have to be updated too. This will be checked soon. |
rfajardo |
3649d 19h |
/minsoc/trunk/ |
