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27 Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, which did not output its data.

The data was being output to doq instead of q, the declared output. doq was also not defined anywhere else.

Icarus Verilog did not detect this, because Verilog-2001 allows internal wires to be used without being defined. To detect this errors, one can define "`default_nettype none". After doing this, Icarus Verilog detected that error and nothing else.

doq changed to q, error corrected.
rfajardo 3872d 17h /minsoc/trunk/
26 On version 34 of the Advanced Debug System the signal debug_tdo_o from the altera_virtual_jtag has changed to debug_tdo_i.

This commit adapts minsoc_top.v accordingly.
rfajardo 3882d 06h /minsoc/trunk/
25 Updated the howto document to adapt minsoc to a new update of the Advanced Debug System.
-Compilation of adv_jtag_bridge needs a Makefile adjustment.
-Simulation and Implementation have to remove a definition on the adbg_defines.v file.

Both adjustments simply removes the new JSP (JTAG Serial Port), which has been included in the new release of the Advanced Debug System.
rfajardo 3886d 22h /minsoc/trunk/
24 E-mail in the documentation has been corrected. rfajardo 3950d 10h /minsoc/trunk/
23 Paragraph minor changes, used in announcement and double checked. rfajardo 3954d 15h /minsoc/trunk/
22 Status progress and howto pdf documents were not commited, there now. rfajardo 3954d 16h /minsoc/trunk/
21 Including the first draft project documentation. How to and status progress docs are now separate from documentation. rfajardo 3954d 17h /minsoc/trunk/
20 minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.

minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.

Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too.
rfajardo 3961d 17h /minsoc/trunk/
19 Documentation update. How To: 7) Examples:
-Spartan 3E Starter Kit no Ethernet has been already tested and is known to work.
-Spartan 3E Starter Kit with Ethernet not yet.
-change of sw/support/orp.ld cannot be done by only commenting and uncommenting line, the instruction, documentation line, which said so has been removed.
-Further possibilities -> Further area optimization possibilities.
rfajardo 3992d 21h /minsoc/trunk/
18 Deprecated comments removed from the file listing files. rfajardo 4024d 22h /minsoc/trunk/
17 Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.
rfajardo 4026d 17h /minsoc/trunk/
16 Further initialization improvement of non-used signals, setting interrupt signals to 0 if module is not used. rfajardo 4031d 20h /minsoc/trunk/
15 Including verified pinout for external spi flash on spartan3a dsp kit to its correspondent ucf constraint file. rfajardo 4032d 14h /minsoc/trunk/
14 Wishbone error signal of Ethernet core was not tied to ground if Ethernet was disabled. Solved now. rfajardo 4040d 21h /minsoc/trunk/
13 Updating spartan3e_starter_kit.ucf so that it does not deliver errors on mapping. Moreover it has been changed to off the shelf only have uart support. Ethernet support and generic JTAG can be added by uncommenting the corresponding lines. rfajardo 4041d 21h /minsoc/trunk/
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.
rfajardo 4044d 13h /minsoc/trunk/
11 External interrupt processing was being run multiple times because:
-external level interrupts have to be cleared
-internal interrupt status register has to be cleared
Since internal interrupt status register was being cleared before external level interrupts clearance, these internal interrupt status was being overwritten inbetween.

Solution:
-move status register reset to end of interrupt handler instead of beginning.

Testbench signal uart_srx initialized now.
rfajardo 4051d 17h /minsoc/trunk/
10 Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v.

With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers.

minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary.
rfajardo 4065d 16h /minsoc/trunk/
9 Tiny change to testbench gain:
-uart_srx is now reg for future testbench serial input to SoC.
rfajardo 4067d 15h /minsoc/trunk/
8 Cosmetic changes to minsoc_bench.v:
-reset and clock initialization are included into the main initial block, it had an own block before
rfajardo 4067d 15h /minsoc/trunk/
7 Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o.
rfajardo 4072d 16h /minsoc/trunk/
6 No implementation relevant changes.

Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.

Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.
rfajardo 4076d 22h /minsoc/trunk/
5 vpi path corrected in how to. rfajardo 4082d 21h /minsoc/trunk/
4 minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.

jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.

Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2)
rfajardo 4082d 21h /minsoc/trunk/
3 Changed documentation
-advice to compile sw/utils before compiling target software
rfajardo 4086d 19h /minsoc/trunk/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4086d 20h /minsoc/trunk/
1 The project was created and the structure was created root 4086d 21h /minsoc/trunk/

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