Subversion Repositories minsoc

[/] [minsoc/] [trunk/] - Rev 85


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3421d 15h /minsoc/trunk/
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 3422d 16h /minsoc/trunk/
83 bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 3433d 21h /minsoc/trunk/
82 problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. rfajardo 3436d 21h /minsoc/trunk/
81 Installation script complete, nice text feedback, output logs and better execution order. rfajardo 3437d 08h /minsoc/trunk/
80 Establishing a better Makefile system for firmwares. rfajardo 3439d 20h /minsoc/trunk/
79 rpath corrected.
required-cygwin-tools: updated
rfajardo 3440d 13h /minsoc/trunk/
78 Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). rfajardo 3440d 13h /minsoc/trunk/
77 New tool requirements for installing Icarus Verilog. rfajardo 3440d 13h /minsoc/trunk/
76 Including a script allowing the installation of MinSoC and all its required tools.

It should be working for all Linuxes and Cygwin.
rfajardo 3440d 13h /minsoc/trunk/
75 Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules and define file of ethmac ip core. rfajardo 3447d 13h /minsoc/trunk/
74 or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined macro) to find out if we need the underscore as prefix to reference C functions (its assembly labels) or not.

except.S and reset.S use CLABLE to call externally defined C functions.

This should avoid problems compiling firmware with old or new toolchain.

support/ updated, reset-nocache.o and reset-icdc.o are dependent on or1200.h
rfajardo 3540d 12h /minsoc/trunk/
73 Makefile does not automatic clean anymore. In Windows rm -f leads to errors and abort synthesis.

minsoc/syn/setup.bat added. Asks for Xilinx settings32|64.bat script and completely implements MinSoC. On completion or error, it holds window open until user input ENTER.

minsoc/sim/modelsim/: *.bat holds window open until user input ENTER.
run_sim.bat asks for target firmware, check if it exists before running simulator. Holds window open and output error message if not found. Does not hold for simulator.
rfajardo 3540d 17h /minsoc/trunk/
72 Adding Windows batch files to run a Modelsim simulation.
-prepare_modelsim.bat, compile_design.bat, run_sim.bat
rfajardo 3540d 18h /minsoc/trunk/
71 Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.
rfajardo 3540d 20h /minsoc/trunk/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, has to be changed:
-pli ../../bench/verilog/vpi/
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3540d 21h /minsoc/trunk/
69 backend update:
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/ now references to inside backend.

-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 3545d 13h /minsoc/trunk/
68 Still one configuration mismatch on minsoc_defines.v:
-orp.ld is defined accordingly
rfajardo 3547d 16h /minsoc/trunk/
67 Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the STARTUP module.

This module is not enabled under the respective minsoc_defines.v. Thus, its pins had to be commented out.
rfajardo 3547d 17h /minsoc/trunk/
66 spartan3e_starter_kit requires special configuration of or1200_r3.

For that, configure script was specially adapted and that is reported on script execution.

For release-1.0 of MinSoC this should not be required, because or1200_r1 already has the
required configuration.
rfajardo 3547d 17h /minsoc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2021, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.