| Rev |
Log message |
Author |
Age |
Path |
| 158 |
Adding de2_115_board port, thanks to Richard Hasha.
Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.
Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.
Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.
prj/srcs extended to include jsp and interconnec_defines.v.
spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now. |
rfajardo |
4487d 13h |
/minsoc/trunk/backend |
| 149 |
Merging differences of release candidate 1.0 revision 140:148 with trunk. |
rfajardo |
4525d 22h |
/minsoc/trunk/backend |
| 144 |
Updating configure scripts. Calling make into the right directories now. |
rfajardo |
4531d 21h |
/minsoc/trunk/backend |
| 142 |
Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.
backend/xxx/configure: compiling firmwares here now. |
rfajardo |
4531d 22h |
/minsoc/trunk/backend |
| 141 |
Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. |
rfajardo |
4531d 22h |
/minsoc/trunk/backend |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4558d 23h |
/minsoc/trunk/backend |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4602d 23h |
/minsoc/trunk/backend |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4603d 00h |
/minsoc/trunk/backend |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4603d 10h |
/minsoc/trunk/backend |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4604d 13h |
/minsoc/trunk/backend |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4607d 01h |
/minsoc/trunk/backend |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4607d 23h |
/minsoc/trunk/backend |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4608d 16h |
/minsoc/trunk/backend |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4608d 17h |
/minsoc/trunk/backend |
| 86 |
Updating configure script messages. |
rfajardo |
4608d 17h |
/minsoc/trunk/backend |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4608d 17h |
/minsoc/trunk/backend |
| 80 |
Establishing a better Makefile system for firmwares. |
rfajardo |
4626d 21h |
/minsoc/trunk/backend |
| 70 |
Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.
Removing timescale definition of minsoc_bench_defines.v files.
Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll
These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi. |
rfajardo |
4727d 22h |
/minsoc/trunk/backend |
| 69 |
backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.
They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.
backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet. |
rfajardo |
4732d 14h |
/minsoc/trunk/backend |
| 68 |
Still one configuration mismatch on minsoc_defines.v:
-MEMORY_ADR_WIDTH now 15
-orp.ld is defined accordingly |
rfajardo |
4734d 18h |
/minsoc/trunk/backend |
