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[/] [minsoc/] [trunk/] [backend/] [altera_3c25_board/] - Rev 158

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158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
rfajardo 3112d 12h /minsoc/trunk/backend/altera_3c25_board/
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 3150d 21h /minsoc/trunk/backend/altera_3c25_board/
144 Updating configure scripts. Calling make into the right directories now. rfajardo 3156d 20h /minsoc/trunk/backend/altera_3c25_board/
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.
rfajardo 3156d 20h /minsoc/trunk/backend/altera_3c25_board/
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 3156d 20h /minsoc/trunk/backend/altera_3c25_board/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3183d 22h /minsoc/trunk/backend/altera_3c25_board/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3227d 22h /minsoc/trunk/backend/altera_3c25_board/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3227d 22h /minsoc/trunk/backend/altera_3c25_board/
96 Some files needed for Altera synthesis javieralso 3228d 09h /minsoc/trunk/backend/altera_3c25_board/
95 Makefile for Altera FPGAs fixed javieralso 3229d 12h /minsoc/trunk/backend/altera_3c25_board/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3231d 23h /minsoc/trunk/backend/altera_3c25_board/

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