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[/] [minsoc/] [trunk/] [backend/] [altera_3c25_board/] - Rev 99

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Rev Log message Author Age Path
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3420d 17h /minsoc/trunk/backend/altera_3c25_board/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3420d 17h /minsoc/trunk/backend/altera_3c25_board/
96 Some files needed for Altera synthesis javieralso 3421d 04h /minsoc/trunk/backend/altera_3c25_board/
95 Makefile for Altera FPGAs fixed javieralso 3422d 07h /minsoc/trunk/backend/altera_3c25_board/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3424d 19h /minsoc/trunk/backend/altera_3c25_board/

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