| Rev |
Log message |
Author |
Age |
Path |
| 168 |
Installation script has an option for advanced or resumed installation.
Advanced mode:
the script only downloads and installs the required tools. Dependency libraries and tools are checked during individual tool compilation. Furthermore, the install directory is not added to the system PATH. You have to do it yourself. Libusb, libftdi and Icarus Verilog are supposed to be installed by the user.
Resumed mode:
the script checks if the dependency libraries and tools are installed before doing anything. It also adds the installation directory to the system PATH variable for bash shells on HOME/.bashrc. Libusb, libftdi and Icarus Verilog are automatically installed for you.
Non standard configuration scripts that require or1200_defines.v to be tweaked will ask before doing so and backup the correspondent files. |
rfajardo |
4331d 23h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 165 |
Board contribution: nexys2_1200 (Thanks to Johan Granath)
spartan3e_starter_kit_eth/minsoc_bench_defines.v: deprecated definition updated |
rfajardo |
4397d 02h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 158 |
Adding de2_115_board port, thanks to Richard Hasha.
Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.
Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.
Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.
prj/srcs extended to include jsp and interconnec_defines.v.
spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now. |
rfajardo |
4488d 16h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 144 |
Updating configure scripts. Calling make into the right directories now. |
rfajardo |
4533d 00h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 142 |
Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.
backend/xxx/configure: compiling firmwares here now. |
rfajardo |
4533d 01h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 141 |
Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. |
rfajardo |
4533d 01h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 105 |
Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. |
rfajardo |
4560d 02h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4604d 03h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4609d 02h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4609d 19h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4609d 20h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 86 |
Updating configure script messages. |
rfajardo |
4609d 20h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4609d 20h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 80 |
Establishing a better Makefile system for firmwares. |
rfajardo |
4628d 00h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 70 |
Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.
Removing timescale definition of minsoc_bench_defines.v files.
Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll
These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi. |
rfajardo |
4729d 01h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
| 69 |
backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.
They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.
backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet. |
rfajardo |
4733d 17h |
/minsoc/trunk/backend/spartan3e_starter_kit_eth/ |
