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[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit_eth/] - Rev 97

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Rev Log message Author Age Path
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3050d 18h /minsoc/trunk/backend/spartan3e_starter_kit_eth/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3055d 17h /minsoc/trunk/backend/spartan3e_starter_kit_eth/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3056d 10h /minsoc/trunk/backend/spartan3e_starter_kit_eth/
87 Synchronizing scripts to behave exactly the same. rfajardo 3056d 11h /minsoc/trunk/backend/spartan3e_starter_kit_eth/
86 Updating configure script messages. rfajardo 3056d 11h /minsoc/trunk/backend/spartan3e_starter_kit_eth/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3056d 11h /minsoc/trunk/backend/spartan3e_starter_kit_eth/
80 Establishing a better Makefile system for firmwares. rfajardo 3074d 15h /minsoc/trunk/backend/spartan3e_starter_kit_eth/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3175d 16h /minsoc/trunk/backend/spartan3e_starter_kit_eth/
69 backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.

backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 3180d 08h /minsoc/trunk/backend/spartan3e_starter_kit_eth/

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