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[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_memory_model.v] - Rev 35

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2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 5305d 11h /minsoc/trunk/bench/verilog/minsoc_memory_model.v

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