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[/] [minsoc/] [trunk/] [bench/] [verilog/] [vpi/] [dbg_comm_vpi.v] - Rev 155

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155 Decreased wait time, for faster simulations. nyawn 3073d 14h /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v
71 Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.
rfajardo 3308d 04h /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 3907d 03h /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v

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