Rev |
Log message |
Author |
Age |
Path |
49 |
Language correction for README.txt. |
rfajardo |
4950d 10h |
/minsoc/trunk/doc/ |
48 |
Clear some old docs that are already ported to MinSOC's Wiki |
ConX. |
4950d 11h |
/minsoc/trunk/doc/ |
40 |
Commiting a contributions directory, which has raw contributions of users. These contributions still have to be adapted to the system in order to work well. However, some users are certainly able to work with these versions.
FAQ: -added new idea to circumvent onboard DLC9 cable problem for adv_jtag_bridge
INSTALL: -gives a hint on how to install the system for Windows
HOWTO: -explains what a ucf file is and how to create it
backend: now we have the first contribution of a ucf file for the ML509 board (thanks to Matthew Hick)
Documentation: THESIS.txt explains to users, willing to tweak/understand the inner behavior of the OR1200 implementation of OpenRISC, what to read in order to get this information. |
rfajardo |
4963d 08h |
/minsoc/trunk/doc/ |
39 |
FAQ:
-Adv_jtag_bridge self test fails?
-included now SoC flow mistakes
-forgetting to upload the bitfile
-leaving clock unconnected
-older information is now under "Known Issues" right below of SoC flow mistakes
Software:
-eth: included eth.h is from drivers and not from this directory. eth.h from this directory is old and has been removed.
-uart: included uart.h is from drivers and not from this directory. uart.h from this directory is old and has been removed. |
rfajardo |
5028d 01h |
/minsoc/trunk/doc/ |
38 |
Small update to HOWTO: advices now to also include the ucf (pinout) file, for forgetful people :-).
FAQ: Added another option (hint) as a solution for people with on-board Xilinx USB cables, which do not reset.
uart.c: now uses the IRQ line definition instead of the line number directly. |
rfajardo |
5063d 00h |
/minsoc/trunk/doc/ |
37 |
README.txt added, describing the installation and set-up processes. Also describing to use the FAQ or forum when you have problems and finally to read minsoc.pdf (the documentation) to understand the system after everything works, to know what to do next.
Clean-up of sw/utils, removing unused sources and files.
Update of sw/drivers/eth.c, direct casting to avoid compile warnings.
FAQ extended and with more links to the threads giving the solutions.
Synthesis examples inform that the firmware tweak for Spartan3E Starter Kit using Ethernet only works for system version up to 35.
minsoc.pdf and webpage now uses FPGA generic and specific codes instead of FPGA independent and dependent codes, because it suits it better. |
rfajardo |
5093d 11h |
/minsoc/trunk/doc/ |
36 |
utils: -adding a 32 to 8 bit Wishbone bridge to connect 8 bit modules to the MinSoC interconnect.
-adding a Linux driver for parallel cables for the adv_jtag_bridge. It circumvents the necessity of privilege to run adv_jtag_bridge with cables xpc3 and xess.
sw/support: support library has been made completely standalone. That means, it is now independent from uClib and/or newlib. Thanks to Wojciech A. Koszek for his contribution on this.
sw/drivers: a driver library has been included, which supply drivers for the OpenRISC timer; and for UART, Ethernet, I2C, and CAN modules from OpenCores.
sw/uart and sw/eth: they don't provide code to control the UART and Ethernet controllers anymore. They use the drivers library instead.
Documentation:
-FAQ extended:
-table of contents
-explanation of how to use the 32 to 8 bit Wishbone bridge
-how to make adv_jtag_bridge work without privilege requirement for xess or xpc3
-explanation of locking problem of xpc_usb cable
-explanation of what to do if the cable is built on-board
-INSTALL:
-patching of gdb only required if version is 6.8, explanation on FAQ now.
-HOWTO:
-instruct to compile drivers library
-remove line numbers information on what to edit, better leave it to be found only by the informed context.
-adv_jtag_bridge execution now without 'sudo'. Note included that 'sudo' is required for Linux and xess or xpc3. Reference to FAQ to avoid this requirement. |
rfajardo |
5094d 07h |
/minsoc/trunk/doc/ |
35 |
minsoc.pdf: -adjusting the date on the page header of MinSoC documentation. It was correct on the front and revision pages, now header adjusted accordingly. |
rfajardo |
5099d 01h |
/minsoc/trunk/doc/ |
34 |
start_server changed: '-t' option of adv_jtag_bridge for vpi connection on simulation removed. or1200_v3 will not pass on CPU self test.
FAQ completed with asked questions since Februrary 2010.
INSTALL informs bsdl files only have to be copied to home directory for Xilinx devices.
synthesis_examples title includes Minimal OpenRISC System on Chip. |
rfajardo |
5108d 09h |
/minsoc/trunk/doc/ |
32 |
Documentation revision 1.1, thanks to Wojciech A. Koszek for many comments on it.
Also updating howto, splitint it in INSTALL, HOWTO, FAQ and synthesis_examples, so it should be more clear now what to do when and not to try too much when you don't need. Like everyone was trying to debug the simulation but didn't even test the regular simulation before. Again thanks to Wojciech A. Koszek for his view on this matter. |
rfajardo |
5130d 09h |
/minsoc/trunk/doc/ |
31 |
Adaption to or1200_r3. It is still important to change or1200_defines.v:
-`define OR1200_BOOT_ADR 32'hf0000100 to `define OR1200_BOOT_ADR 32'h00000100 |
rfajardo |
5185d 16h |
/minsoc/trunk/doc/ |
30 |
minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek.
howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file.
Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD. |
rfajardo |
5228d 14h |
/minsoc/trunk/doc/ |
29 |
Finishing the howto for Spartan3E Starter Kit with Ethernet. Last hint, change uart baudrate to 9600 to avoid the baudrate skew problem due to truncation.
Following the howto to implement Ethernet on Spartan3E Starter Kit will work flawlessly now. |
rfajardo |
5270d 14h |
/minsoc/trunk/doc/ |
28 |
1) Period calculations through 1/freq on testbench use now a numerator definition in order to extract nano seconds of the divisions. Previously the number 1e9 was being repeatedly typed as numerator, now FREQ_NUM_FOR_NS is used.
2) There is a possibility of enabling the GENERIC_CLOCK_DIVISION for the testbench, so that you can test the outcome of different system clock inputs and internal clock adjustments. To do so, NO_CLOCK_DIVISION definition of minsoc_bench_defines.v has to be commented out.
-This also requested the initialization of the internal registers clk_int and clock_divisor of the minsoc_clock_manager.v, this is made by the testbench in case the NO_CLOCK_DIVISION definition is NOT defined.
3) Howto part of implementing Ethernet for the Spartan3E Starter Kit has been completely described. (Chapter 7, subitem 3) |
rfajardo |
5271d 09h |
/minsoc/trunk/doc/ |
25 |
Updated the howto document to adapt minsoc to a new update of the Advanced Debug System.
-Compilation of adv_jtag_bridge needs a Makefile adjustment.
-Simulation and Implementation have to remove a definition on the adbg_defines.v file.
Both adjustments simply removes the new JSP (JTAG Serial Port), which has been included in the new release of the Advanced Debug System. |
rfajardo |
5300d 14h |
/minsoc/trunk/doc/ |
24 |
E-mail in the documentation has been corrected. |
rfajardo |
5364d 03h |
/minsoc/trunk/doc/ |
23 |
Paragraph minor changes, used in announcement and double checked. |
rfajardo |
5368d 07h |
/minsoc/trunk/doc/ |
22 |
Status progress and howto pdf documents were not commited, there now. |
rfajardo |
5368d 08h |
/minsoc/trunk/doc/ |
21 |
Including the first draft project documentation. How to and status progress docs are now separate from documentation. |
rfajardo |
5368d 10h |
/minsoc/trunk/doc/ |
20 |
minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.
minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.
Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too. |
rfajardo |
5375d 10h |
/minsoc/trunk/doc/ |
19 |
Documentation update. How To: 7) Examples:
-Spartan 3E Starter Kit no Ethernet has been already tested and is known to work.
-Spartan 3E Starter Kit with Ethernet not yet.
-change of sw/support/orp.ld cannot be done by only commenting and uncommenting line, the instruction, documentation line, which said so has been removed.
-Further possibilities -> Further area optimization possibilities. |
rfajardo |
5406d 14h |
/minsoc/trunk/doc/ |
17 |
Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.
send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)
If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module. |
rfajardo |
5440d 09h |
/minsoc/trunk/doc/ |
12 |
1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now. |
rfajardo |
5458d 05h |
/minsoc/trunk/doc/ |
6 |
No implementation relevant changes.
Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.
Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v. |
rfajardo |
5490d 14h |
/minsoc/trunk/doc/ |
5 |
vpi path corrected in how to. |
rfajardo |
5496d 13h |
/minsoc/trunk/doc/ |
4 |
minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.
jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.
Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2) |
rfajardo |
5496d 14h |
/minsoc/trunk/doc/ |
3 |
Changed documentation
-advice to compile sw/utils before compiling target software |
rfajardo |
5500d 12h |
/minsoc/trunk/doc/ |
2 |
First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit |
rfajardo |
5500d 12h |
/minsoc/trunk/doc/ |