| Rev |
Log message |
Author |
Age |
Path |
| 24 |
E-mail in the documentation has been corrected. |
rfajardo |
5365d 06h |
/minsoc/trunk/doc/minsoc.pdf |
| 23 |
Paragraph minor changes, used in announcement and double checked. |
rfajardo |
5369d 10h |
/minsoc/trunk/doc/minsoc.pdf |
| 21 |
Including the first draft project documentation. How to and status progress docs are now separate from documentation. |
rfajardo |
5369d 12h |
/minsoc/trunk/doc/minsoc.pdf |
| 20 |
minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.
minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.
Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too. |
rfajardo |
5376d 13h |
/minsoc/trunk/doc/minsoc.pdf |
| 19 |
Documentation update. How To: 7) Examples:
-Spartan 3E Starter Kit no Ethernet has been already tested and is known to work.
-Spartan 3E Starter Kit with Ethernet not yet.
-change of sw/support/orp.ld cannot be done by only commenting and uncommenting line, the instruction, documentation line, which said so has been removed.
-Further possibilities -> Further area optimization possibilities. |
rfajardo |
5407d 17h |
/minsoc/trunk/doc/minsoc.pdf |
| 17 |
Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.
send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)
If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module. |
rfajardo |
5441d 12h |
/minsoc/trunk/doc/minsoc.pdf |
| 12 |
1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now. |
rfajardo |
5459d 08h |
/minsoc/trunk/doc/minsoc.pdf |
| 6 |
No implementation relevant changes.
Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.
Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v. |
rfajardo |
5491d 17h |
/minsoc/trunk/doc/minsoc.pdf |
| 5 |
vpi path corrected in how to. |
rfajardo |
5497d 16h |
/minsoc/trunk/doc/minsoc.pdf |
| 4 |
minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.
jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.
Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2) |
rfajardo |
5497d 16h |
/minsoc/trunk/doc/minsoc.pdf |
| 3 |
Changed documentation
-advice to compile sw/utils before compiling target software |
rfajardo |
5501d 14h |
/minsoc/trunk/doc/minsoc.pdf |
| 2 |
First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit |
rfajardo |
5501d 15h |
/minsoc/trunk/doc/minsoc.pdf |
