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35 minsoc.pdf: -adjusting the date on the page header of MinSoC documentation. It was correct on the front and revision pages, now header adjusted accordingly. rfajardo 3828d 00h /minsoc/trunk/doc/minsoc.pdf
32 Documentation revision 1.1, thanks to Wojciech A. Koszek for many comments on it.

Also updating howto, splitint it in INSTALL, HOWTO, FAQ and synthesis_examples, so it should be more clear now what to do when and not to try too much when you don't need. Like everyone was trying to debug the simulation but didn't even test the regular simulation before. Again thanks to Wojciech A. Koszek for his view on this matter.
rfajardo 3859d 08h /minsoc/trunk/doc/minsoc.pdf
30 minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek.

howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file.

Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD.
rfajardo 3957d 13h /minsoc/trunk/doc/minsoc.pdf
24 E-mail in the documentation has been corrected. rfajardo 4093d 02h /minsoc/trunk/doc/minsoc.pdf
23 Paragraph minor changes, used in announcement and double checked. rfajardo 4097d 06h /minsoc/trunk/doc/minsoc.pdf
21 Including the first draft project documentation. How to and status progress docs are now separate from documentation. rfajardo 4097d 08h /minsoc/trunk/doc/minsoc.pdf
20 minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.

minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.

Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too.
rfajardo 4104d 09h /minsoc/trunk/doc/minsoc.pdf
19 Documentation update. How To: 7) Examples:
-Spartan 3E Starter Kit no Ethernet has been already tested and is known to work.
-Spartan 3E Starter Kit with Ethernet not yet.
-change of sw/support/orp.ld cannot be done by only commenting and uncommenting line, the instruction, documentation line, which said so has been removed.
-Further possibilities -> Further area optimization possibilities.
rfajardo 4135d 13h /minsoc/trunk/doc/minsoc.pdf
17 Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.
rfajardo 4169d 08h /minsoc/trunk/doc/minsoc.pdf
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.
rfajardo 4187d 04h /minsoc/trunk/doc/minsoc.pdf
6 No implementation relevant changes.

Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.

Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.
rfajardo 4219d 13h /minsoc/trunk/doc/minsoc.pdf
5 vpi path corrected in how to. rfajardo 4225d 12h /minsoc/trunk/doc/minsoc.pdf
4 minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.

jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.

Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2)
rfajardo 4225d 13h /minsoc/trunk/doc/minsoc.pdf
3 Changed documentation
-advice to compile sw/utils before compiling target software
rfajardo 4229d 11h /minsoc/trunk/doc/minsoc.pdf
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4229d 11h /minsoc/trunk/doc/minsoc.pdf

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