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Rev Log message Author Age Path
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 4536d 02h /minsoc/trunk/prj/scripts/
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!		 rfajardo 4562d 20h /minsoc/trunk/prj/scripts/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.		 rfajardo 4562d 23h /minsoc/trunk/prj/scripts/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4570d 02h /minsoc/trunk/prj/scripts/
96 Some files needed for Altera synthesis javieralso 4607d 14h /minsoc/trunk/prj/scripts/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4612d 04h /minsoc/trunk/prj/scripts/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4612d 20h /minsoc/trunk/prj/scripts/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4612d 21h /minsoc/trunk/prj/scripts/

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