OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [prj/] [src/] - Rev 158

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
rfajardo 4466d 17h /minsoc/trunk/prj/src/
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 4511d 01h /minsoc/trunk/prj/src/
96 Some files needed for Altera synthesis javieralso 4582d 14h /minsoc/trunk/prj/src/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4587d 19h /minsoc/trunk/prj/src/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4587d 19h /minsoc/trunk/prj/src/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4587d 21h /minsoc/trunk/prj/src/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.