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[/] [minsoc/] [trunk/] [prj] - Rev 158

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158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
rfajardo 3188d 23h /minsoc/trunk/prj
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 3233d 08h /minsoc/trunk/prj
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!
rfajardo 3260d 02h /minsoc/trunk/prj
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.
rfajardo 3260d 05h /minsoc/trunk/prj
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 3267d 08h /minsoc/trunk/prj
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3304d 10h /minsoc/trunk/prj
96 Some files needed for Altera synthesis javieralso 3304d 21h /minsoc/trunk/prj
95 Makefile for Altera FPGAs fixed javieralso 3306d 00h /minsoc/trunk/prj
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 3308d 08h /minsoc/trunk/prj
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3308d 11h /minsoc/trunk/prj
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3309d 10h /minsoc/trunk/prj
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 3310d 01h /minsoc/trunk/prj
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 3310d 01h /minsoc/trunk/prj
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3310d 02h /minsoc/trunk/prj
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3310d 03h /minsoc/trunk/prj

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