OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [altera_pll.v] - Rev 88

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something. rfajardo 3551d 18h /minsoc/trunk/rtl/verilog/altera_pll.v
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 3552d 00h /minsoc/trunk/rtl/verilog/altera_pll.v
56 Macros for all Altera family devices and pll instantiation javieralso 3559d 12h /minsoc/trunk/rtl/verilog/minsoc_pll.v
52 Altera ALTPLL Megafunction Instantiation javieralso 3569d 14h /minsoc/trunk/rtl/verilog/minsoc_pll.v

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.