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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Rev 56

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56 Macros for all Altera family devices and pll instantiation javieralso 3131d 23h /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v
52 Altera ALTPLL Megafunction Instantiation javieralso 3142d 01h /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 3712d 10h /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v

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