OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_clock_manager.v] - Rev 62

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 3389d 05h /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v
56 Macros for all Altera family devices and pll instantiation javieralso 3396d 17h /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v
52 Altera ALTPLL Megafunction Instantiation javieralso 3406d 19h /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 3977d 04h /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.