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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_startup/] - Rev 20

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Rev Log message Author Age Path
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.
rfajardo 3687d 20h /minsoc/trunk/rtl/verilog/minsoc_startup/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 3730d 03h /minsoc/trunk/rtl/verilog/minsoc_startup/

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