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30 minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek.

howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file.

Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD.
rfajardo 4492d 00h /minsoc/trunk
29 Finishing the howto for Spartan3E Starter Kit with Ethernet. Last hint, change uart baudrate to 9600 to avoid the baudrate skew problem due to truncation.

Following the howto to implement Ethernet on Spartan3E Starter Kit will work flawlessly now.
rfajardo 4533d 23h /minsoc/trunk
28 1) Period calculations through 1/freq on testbench use now a numerator definition in order to extract nano seconds of the divisions. Previously the number 1e9 was being repeatedly typed as numerator, now FREQ_NUM_FOR_NS is used.

2) There is a possibility of enabling the GENERIC_CLOCK_DIVISION for the testbench, so that you can test the outcome of different system clock inputs and internal clock adjustments. To do so, NO_CLOCK_DIVISION definition of minsoc_bench_defines.v has to be commented out.
-This also requested the initialization of the internal registers clk_int and clock_divisor of the minsoc_clock_manager.v, this is made by the testbench in case the NO_CLOCK_DIVISION definition is NOT defined.

3) Howto part of implementing Ethernet for the Spartan3E Starter Kit has been completely described. (Chapter 7, subitem 3)
rfajardo 4534d 19h /minsoc/trunk
27 Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, which did not output its data.

The data was being output to doq instead of q, the declared output. doq was also not defined anywhere else.

Icarus Verilog did not detect this, because Verilog-2001 allows internal wires to be used without being defined. To detect this errors, one can define "`default_nettype none". After doing this, Icarus Verilog detected that error and nothing else.

doq changed to q, error corrected.
rfajardo 4549d 20h /minsoc/trunk
26 On version 34 of the Advanced Debug System the signal debug_tdo_o from the altera_virtual_jtag has changed to debug_tdo_i.

This commit adapts minsoc_top.v accordingly.
rfajardo 4559d 08h /minsoc/trunk
25 Updated the howto document to adapt minsoc to a new update of the Advanced Debug System.
-Compilation of adv_jtag_bridge needs a Makefile adjustment.
-Simulation and Implementation have to remove a definition on the adbg_defines.v file.

Both adjustments simply removes the new JSP (JTAG Serial Port), which has been included in the new release of the Advanced Debug System.
rfajardo 4564d 00h /minsoc/trunk
24 E-mail in the documentation has been corrected. rfajardo 4627d 13h /minsoc/trunk
23 Paragraph minor changes, used in announcement and double checked. rfajardo 4631d 17h /minsoc/trunk
22 Status progress and howto pdf documents were not commited, there now. rfajardo 4631d 18h /minsoc/trunk
21 Including the first draft project documentation. How to and status progress docs are now separate from documentation. rfajardo 4631d 19h /minsoc/trunk

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