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[/] [minsoc/] [trunk] - Rev 89

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89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 3311d 10h /minsoc/trunk
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3311d 11h /minsoc/trunk
87 Synchronizing scripts to behave exactly the same. rfajardo 3311d 12h /minsoc/trunk
86 Updating configure script messages. rfajardo 3311d 12h /minsoc/trunk
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3311d 12h /minsoc/trunk
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 3312d 13h /minsoc/trunk
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 3323d 18h /minsoc/trunk
82 minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. rfajardo 3326d 17h /minsoc/trunk
81 Installation script complete, nice text feedback, output logs and better execution order. rfajardo 3327d 04h /minsoc/trunk
80 Establishing a better Makefile system for firmwares. rfajardo 3329d 16h /minsoc/trunk
79 minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated
rfajardo 3330d 09h /minsoc/trunk
78 minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). rfajardo 3330d 09h /minsoc/trunk
77 New tool requirements for installing Icarus Verilog. rfajardo 3330d 10h /minsoc/trunk
76 Including a script allowing the installation of MinSoC and all its required tools.

It should be working for all Linuxes and Cygwin.
rfajardo 3330d 10h /minsoc/trunk
75 Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules and define file of ethmac ip core. rfajardo 3337d 10h /minsoc/trunk
74 or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined macro) to find out if we need the underscore as prefix to reference C functions (its assembly labels) or not.

except.S and reset.S use CLABLE to call externally defined C functions.

This should avoid problems compiling firmware with old or new toolchain.

support/common.mk updated, reset-nocache.o and reset-icdc.o are dependent on or1200.h
rfajardo 3430d 08h /minsoc/trunk
73 Makefile does not automatic clean anymore. In Windows rm -f leads to errors and abort synthesis.

minsoc/syn/setup.bat added. Asks for Xilinx settings32|64.bat script and completely implements MinSoC. On completion or error, it holds window open until user input ENTER.

minsoc/sim/modelsim/: *.bat holds window open until user input ENTER.
run_sim.bat asks for target firmware, check if it exists before running simulator. Holds window open and output error message if not found. Does not hold for simulator.
rfajardo 3430d 14h /minsoc/trunk
72 Adding Windows batch files to run a Modelsim simulation.
-prepare_modelsim.bat, compile_design.bat, run_sim.bat
rfajardo 3430d 15h /minsoc/trunk
71 Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.
rfajardo 3430d 17h /minsoc/trunk
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3430d 17h /minsoc/trunk

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