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93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4604d 13h /minsoc/trunk
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4605d 11h /minsoc/trunk
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4605d 12h /minsoc/trunk
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4606d 03h /minsoc/trunk
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4606d 03h /minsoc/trunk
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4606d 04h /minsoc/trunk
87 Synchronizing scripts to behave exactly the same. rfajardo 4606d 05h /minsoc/trunk
86 Updating configure script messages. rfajardo 4606d 05h /minsoc/trunk
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4606d 05h /minsoc/trunk
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 4607d 06h /minsoc/trunk
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 4618d 11h /minsoc/trunk
82 minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. rfajardo 4621d 10h /minsoc/trunk
81 Installation script complete, nice text feedback, output logs and better execution order. rfajardo 4621d 21h /minsoc/trunk
80 Establishing a better Makefile system for firmwares. rfajardo 4624d 10h /minsoc/trunk
79 minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated
rfajardo 4625d 02h /minsoc/trunk
78 minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). rfajardo 4625d 03h /minsoc/trunk
77 New tool requirements for installing Icarus Verilog. rfajardo 4625d 03h /minsoc/trunk
76 Including a script allowing the installation of MinSoC and all its required tools.

It should be working for all Linuxes and Cygwin.
rfajardo 4625d 03h /minsoc/trunk
75 Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules and define file of ethmac ip core. rfajardo 4632d 03h /minsoc/trunk
74 or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined macro) to find out if we need the underscore as prefix to reference C functions (its assembly labels) or not.

except.S and reset.S use CLABLE to call externally defined C functions.

This should avoid problems compiling firmware with old or new toolchain.

support/common.mk updated, reset-nocache.o and reset-icdc.o are dependent on or1200.h
rfajardo 4725d 02h /minsoc/trunk
73 Makefile does not automatic clean anymore. In Windows rm -f leads to errors and abort synthesis.

minsoc/syn/setup.bat added. Asks for Xilinx settings32|64.bat script and completely implements MinSoC. On completion or error, it holds window open until user input ENTER.

minsoc/sim/modelsim/: *.bat holds window open until user input ENTER.
run_sim.bat asks for target firmware, check if it exists before running simulator. Holds window open and output error message if not found. Does not hold for simulator.
rfajardo 4725d 07h /minsoc/trunk
72 Adding Windows batch files to run a Modelsim simulation.
-prepare_modelsim.bat, compile_design.bat, run_sim.bat
rfajardo 4725d 08h /minsoc/trunk
71 Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.
rfajardo 4725d 10h /minsoc/trunk
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 4725d 11h /minsoc/trunk
69 backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.

backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 4730d 02h /minsoc/trunk
68 Still one configuration mismatch on minsoc_defines.v:
-MEMORY_ADR_WIDTH now 15
-orp.ld is defined accordingly
rfajardo 4732d 06h /minsoc/trunk
67 Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the STARTUP module.

This module is not enabled under the respective minsoc_defines.v. Thus, its pins had to be commented out.
rfajardo 4732d 06h /minsoc/trunk
66 spartan3e_starter_kit requires special configuration of or1200_r3.

For that, configure script was specially adapted and that is reported on script execution.

For release-1.0 of MinSoC this should not be required, because or1200_r1 already has the
required configuration.
rfajardo 4732d 07h /minsoc/trunk
65 Files missing in the last commit.
backend/std/configure
sw: eth, uart and driver Makefiles
rfajardo 4732d 08h /minsoc/trunk
64 firmware makefiles:
-every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you.
-TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually.

Makefile system for synthesis:
-the dependency for every implementation step has been checked and is working fine.
-Makefile plus support files have been moved to minsoc/syn/src
-make usage is still under syn through files generated by backend bashscripts
Backend:
-files under backend are target specific files used for the system to work
-firmware compilation
-system simulation
-system implementation
-This directory is populated by visiting one of its subdirectories and typing ./configure

backend/spartan3a_dsp_kit:
-working on FPGA

backend/spartan3e_starter_kit:
-has to be tested

backend/ml509:
-missing files have to be copied and adapted, configure script has to be copied and adapted

backend/std:
-include files necessary for firmware compilation and system configuration
-it does not include files for synthesis and is not synthesizable
rfajardo 4732d 10h /minsoc/trunk

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