OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc] - Rev 161

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
161 Correcting configure parameters of adv_jtag_bridge on installation script. rfajardo 3827d 23h /minsoc
160 Typo in minsoc-install.sh script. Adv_jtag_bridge was not configuring correctly. rfajardo 3827d 23h /minsoc
159 Updated constraint file for de2_115 board. (Richard Hasha) rfajardo 3827d 23h /minsoc
158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
rfajardo 3829d 15h /minsoc
157 Removed obsolete file; the changes in this version have been merged into
the mainline advanced debug system version 3.0 and higher.
nyawn 3835d 10h /minsoc
156 Added hardware watchpoint indicators to debug unit break input, to allow
the debugger to break when a hardware watchpoint is triggered.
nyawn 3835d 10h /minsoc
155 Decreased wait time, for faster simulations. nyawn 3835d 10h /minsoc
154 Modified to use the new autotools support in the advanced debug system v3.0. nyawn 3835d 11h /minsoc
153 Updating installation script to download minsoc from this branche, verilator, instead of rc-1.0. rfajardo 3868d 00h /minsoc
152 Roll back to retrieve minsoc from branches/rc-1.0. rfajardo 3868d 00h /minsoc
151 Creating tag release-1.0 from revision 150 of branches/rc-1.0. rfajardo 3868d 00h /minsoc
150 Updating installation script to retrieve minsoc from tags/release-1.0. rfajardo 3868d 00h /minsoc
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 3868d 01h /minsoc
148 Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness. rfajardo 3872d 21h /minsoc
147 Updating minsoc_bench.v to correctly acquire uart data.

Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
-Eth and Uart firmwares also had a carriage return after the end of line, also removed.

Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT

run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.

minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.
rfajardo 3872d 23h /minsoc
146 Importing 'Xilinx Microblaze Dev. Kit 1600E Edition' board configuration directory. ConX. 3873d 04h /minsoc
145 minsoc_bench_core.v and minsoc_bench_clock.v left only on verilator branche. It will develop there until it is ported for inclusion into trunk. RC-1.0 is now clean of it. rfajardo 3873d 13h /minsoc
144 Updating configure scripts. Calling make into the right directories now. rfajardo 3874d 00h /minsoc
143 Compiling firmwares in board configuration scripts instead of on global minsoc setup. rfajardo 3874d 00h /minsoc
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.
rfajardo 3874d 00h /minsoc

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.